1. Field of the Invention
The present invention relates to overvoltage protection for integrated circuits, and in particular, to protection against MOSFET oxide damage caused by plasma-induced electrical charges.
2. Description of the Related Art
As design and fabrication technologies have advanced for integrated circuit (ICs) with metal-oxide semiconductor field effect transistors (MOSFETs), particularly in the area of submicron analog MOSFET ICs, damage to the MOSFET gate oxide caused by plasma-induced electrical charges has become a serious problem. As is well known in the art, great care must be taken to avoid "antenna" effects by insuring that metallization which directly contacts the polysilicon gate terminals of the MOSFETs is not too long, i.e., that the surface area of such metallization is not so large that excessive electrical charges collect and discharge through small gate oxide areas.
One technique which has been used to overcome this problem is to physically break up the metallization areas and interconnect them by way of jumpers made from a subsequent layer of metallization. That way, even if the initial metallization process results in excessive charge build-up, no discharge will take place through sensitive MOSFET gate oxides. However, this technique is not completely satisfactory for a number of reasons. First, an additional layer of metallization, if not already required, becomes required to fabricate the jumpers. Also, care must be taken to ensure that any excessive charge build-up in the first layer of metallization is dissipated prior to the interconnection(s) via jumpers. Further, the introduction of additional physical interconnections in the form of the jumpers increases the potential for failures caused by bad connections.
Accordingly, it would be desirable to have an improved technique for avoiding, or at least minimizing, MOSFET gate oxide damage caused by charge collection by metallization layers during wafer processing.